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COMPARISON OF 2-PHASE LATCH CONFIGURATIONS FOR PIPELINED PROCESSORS IN MOS VLSI - CASE-STUDY - A CMOS SYSTOLIC MULTIPLIER
IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS.
v.
137.
no.
4.
1990-08.
p.
261 -
265...
issn:
0956-3768
.
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